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Renesas Electronics /R7FA6M1AD /DBG /DBGSTOPCR

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Interpret as DBGSTOPCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DBGSTOP_IWDT 0 (0)DBGSTOP_WDT 0DBGSTOP_LVD 0 (0)DBGSTOP_RPER 0 (0)DBGSTOP_RECCR

DBGSTOP_RPER=0, DBGSTOP_IWDT=0, DBGSTOP_WDT=0, DBGSTOP_RECCR=0

Description

Debug Stop Control Register

Fields

DBGSTOP_IWDT

Mask bit for IWDT reset/interrupt

0 (0): Mask IWDT reset/interrupt

1 (1): Enable IWDT reset
DBGSTOP_WDT

Mask bit for WDT reset/interrupt

0 (0): Mask WDT reset/interrupt

1 (1): Enable WDT reset
DBGSTOP_LVD

b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask)
DBGSTOP_RPER

Mask bit for RAM parity error reset/interrupt

0 (0): Enable RAM parity error reset/interrupt

1 (1): Mask RAM parity error reset/interrupt
DBGSTOP_RECCR

Mask bit for RAM ECC error reset/interrupt

0 (0): Enable RAM ECC error reset/interrupt

1 (1): Mask RAM ECC error reset/interrupt

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data